The present invention relates to a demodulation circuit for a digital modulated signal used to transmit or record/reproduce digital signals.
When a digital signal is to be transmitted or recorded, it is necessary to convert or modulate the signal into a form suitable to the transmission path or the recording medium.
Modulation techniques for digital signals, the MFM (Modified Frequency Modulation) technique, the Miller.sup.2 technique, and the ZM (Zero Modulation) technique are known.
A digital signal modulated by the MFM technique has two possible inversion locations. That is to say, the digital signal modulated by the MFM technique is inverted in the middle of a data transfer period or inverted in synchronism with a data transfer period. In case of a datum "1", for example, the digital signal is inverted in the middle of a transfer period of the data "1". When a datum "0" is followed by another datum "0", the digital signal is inverted at the boundary between those data, i.e., at such a location as to be in synchronism with the transfer period. For a single datum "0", the digital signal is not inverted.
The MFM signal has features that the difference between the maximum value of the inversion interval of a signal and its minimum value is large and the timing information (clock) can easily be extracted. And the MFM signal is used in a number of apparatuses. The Miller.sup.2 signal is nearly the same as the MFM signal. The MFM signal will now be described by referring to FIG. 2.
In FIG. 2, a waveform 2A represents an example of an NRZ signal before modulation. A waveform 2B represents the NRZ signal after the MFM modulation. In the MFM modulation technique, inversion in polarity is associated with "1" of the input signal 2A, while non-inversion in polarity is associated with "0". When two data "0", appear in succession, the polarity is inverted at the connection point between two data.
For demodulating this MFM-modulated signal, the clock signal must be extracted from the signal 2B first of all. For example, an edge signal 2C corresponding to the rising edge/falling edge of data is produced from the signal 2B. From the signal 2C, clock pulses 2D are produced by using a tank circuit or a PLL circuit or the like. Succeedingly, the clock pulses 2D undergo frequency demultiplication with a ratio of 2 to produce pulses 2E and 2F having opposite phases with respect to each other. One of these pulses, 2E for example is used as a latch pulse 2G. The latch pulses 2G latches the edge signal 2C, the original NRZ signal being thus modulated as a signal 2H.
However, it is not known which pulse of 2E and 2F should be selected as the latch pulse. It must be decided by other information for selection.
Two methods have been proposed as the method for deciding the latch pulse. In accordance with one of these methods, a fixed pattern such as information of "1" and/or "0" within a predetermined period is recorded, and the latch pulse is selected on the basis of this information. This method is used in apparatuses such as magnetic disks.
However, this method has two drawbacks described below. The first drawback will now be described. Since redundancy for inserting a fixed pattern into the original NRZ signal is needed, complicated signal processing is required for the modulation circuit. In addition, a circuit for detecting the fixed pattern is needed in the demodulation circuit. The second drawback will now be described. A fixed pattern is inserted only intermittently at long time intervals. Should the number of clocks change due to disturbance such as dropout, all data appearing since then until the detection of the fixed pattern are demodulated erroneously.
As a second method for deciding the latch pulse, a method using the conversion rule of the MFM signal is proposed in J-P-B No. 54-38884, for example. A method for deciding the latch pulse using the conversion rule of the Miller.sup.2 signal is proposed in J-P-A No. 52-114206, for example.
When the conversion rule of the MFM signal is used, the maximum value of an interval during which the polarity of the MFM signal is not inverted, i.e., a term between polarity conversion points is equal to four repetition periods of the clock pulse 2D. This maximum value is obtained only when a pattern "101" appears in the original NRZ signal. This pattern corresponds to a pattern "10001" in the edge signal 2C. In the waveform of FIG. 2, a pattern formed from time t.sub.2 to time t.sub.8 is "10001". In case this pattern has been detected, therefore, it is possible to define a correct latch pulse from a phase (time t.sub.7) where the last information "1" of the pattern "10001" of the edge signal is latched.
That is to say, the pulse 2E is decided to be the latch pulse 2G in case of FIG. 2.
If the condition of the apparatus or the recording medium is aggravated, however, an erroneous "10001" pattern might appear in the edge signal of reproduced data. When the second method is used, therefore, there is a possibility that an erroneous latch pulse is selected. This error causes a problem that all data become erroneous until the next correct pattern "10001" is reproduced.
FIG. 3 shows an original NRZ signal 3A and an MFM signal 3B obtained when an erroneous pattern "10001" is produced in the edge signal because of an error caused in the MFM reproduced signal.
Although the MFM reproduced signal 3B should change to "1" at time t.sub.5 as indicated by broken lines, the signal 3B erroneously remains at "0". Therefore, the detected edge signal 3C produces an erroneous pattern "10001" between time t.sub.3 and time t.sub.9.
From this detected edge signal 3C, a clock pulse 3D is extracted. Waveforms 3E and 3F represent pulse obtained by applying frequency demultiplication to the clock pulses 3D. One of these waveforms, 3E for example is selected as a latch pulse 3G. If an erroneous pattern "10001" of the detected edge signal is detected at a location p of the MFM signal 3B, the output 3G of the latch pulse is changed from 3E to 3F at time t.sub.7. Since then, all data are erroneously demodulated, an erroneous NRZ signal 3H being thus outputted. In the illustrated NRZ signal 3H, portions indicated by marks x are erroneous.
Such a drawback is caused not only in a demodulation circuit for the MFM signal but also in demodulation circuits for the Miller.sup.2 signal and the ZM signal.
Assuming now that the data transfer period of the modulated digital signal is T.sub.b in an example of a prior art circuit for demodulating digital signals modulated by the MFM technique and recorded on a recording medium, the repetition period of the clock 3D required for the demodulation circuit is set to half of T.sub.b as described in J-P-B No. 54-38884, for example.
When the MFM digital modulation technique is used, the input digital signal has the same transfer speed as that of the digital signal after modulation, the modulation technique being thus suitable to high speed recording. For discriminating a datum "1" from a datum "0", however, phase difference within one repetition period is used. Accordingly, an interval for discriminating a datum, i.e., a so-called detection window width becomes T.sub.b /2. As a result, the frequency becomes as high as 2/T.sub.b.
In the above described prior art, disposal for a case where very high speed clocks are needed is not considered in view of the fact that the clock frequency is twice as high as the data transfer speed. In a digital VTR needing high speed recording as high as 100 to 150 Mb/s per channel, for example, the clock frequency becomes 200 to 300 MHZ. Accordingly, the waveform transmission on the substrate circuit becomes difficult because of waveform distortion, attenuation and the like. In addition, the corresponding components become expensive. Because of these problems on mounting, the above described prior art was not put into practical use for such high-speed recording.
These problems were caused in not only demodulation circuits for MFM signals but also in demodulation circuits for Miller.sup.2 signals, ZM signals and the like.